Semiconductor Capex Cycle: WFE, Inventory Whips, and Timing

Key Takeaways

• Semiconductor capex cycle drives capital intensity from roughly 10 percent in a downcycle to 20–25 percent (or more) at cycle peak; tracking WFE bookings from SEMI provides the leading signal 12–24 months ahead of silicon output changes.
• The inventory whip effect means channel destocking at fabless customers (Nvidia, AMD, Qualcomm) can suppress wafer demand for two to four quarters even after end-market demand stabilizes, amplifying the cycle's amplitude.
• A common mistake is treating capex announcements as straightforwardly bullish; a capex hike at the end of a long upcycle signals over-investment, while the same hike at low utilization signals genuine capacity-constrained demand.
• Memory and leading-edge logic cycles are not synchronized, DRAM and NAND can be in deep downturn while AI accelerator demand drives a leading-edge logic upcycle, as occurred in 2023–2024.

What It Is

The semiconductor capex cycle is the recurring pattern of investment in fab capacity, equipment, and process nodes by foundries (TSMC, Samsung Foundry, Intel Foundry, GlobalFoundries) and integrated device manufacturers (Intel, Samsung, SK Hynix, Micron, Texas Instruments). Wafer fab equipment (WFE) spending is the upstream demand signal, and SEMI publishes the global WFE market quarterly.

In the upcycle, capital intensity (capex divided by revenue) for leading-edge logic and memory players typically runs in the 20 to 25 percent range, sometimes higher. In the downcycle, it can fall toward 10 percent as new tool orders are deferred and existing fabs run hot.

The Intuition

Building a fab is a multi-year, multi-billion-dollar bet against demand that will not exist for three to five years. Once the construction commitment is made, equipment orders ramp, and silicon eventually flows. The same fixed-cost engine that produces high gross margins on the way up produces brutal under-absorption on the way down.

Compounding the swing, downstream customers (PC, smartphone, datacenter, auto, industrial) order ahead during shortages and double-order during scarcity. When demand softens, those orders are canceled and inventories drain through the channel. The bullwhip effect at the wafer level can be several times the amplitude of end-demand changes.

How It Works

Track the cycle through three layers of data.

Capital intensity = Capex / Revenue
WFE growth = Year-over-year change in equipment shipments (SEMI)
Inventory days = (Inventory / COGS) * 365
Book-to-bill = New orders / Billed shipments (>1.0 = expanding, <1.0 = contracting)

A standard cycle plays out roughly as follows. End demand strengthens, lead times extend, customers place safety orders, fabs run at high utilization, gross margins peak, capex announcements rise, WFE bookings surge, book-to-bill exceeds 1.0. New capacity comes online roughly 12 to 24 months after the order, just as end demand is slowing. Channel inventories build, lead times normalize, orders are pulled, capex is cut, gross margins compress, book-to-bill falls below 1.0, and the cycle troughs.

For memory (DRAM, NAND), the cycle is shorter and sharper because production is more commodified and customers (mainly hyperscalers, smartphone OEMs, PC OEMs) can shift quickly. For leading-edge logic, the cycle is longer because design wins are stickier and node transitions take years.

Worked Example

Consider a hypothetical foundry. In year one, revenue is 60 billion dollars, capex is 14 billion, and gross margin is 53 percent. In year two, AI accelerator demand surges. Revenue rises to 75 billion, capex is announced at 30 billion, and gross margin holds at 53 percent.

Year 1 capital intensity = 14 / 60 = 23 percent
Year 2 capital intensity = 30 / 75 = 40 percent

The 40 percent ratio is anomalously high and signals a major node ramp. Investors will model the depreciation flow-through. If 30 billion of capex depreciates over six years, annual D&A rises by 5 billion in year three and beyond. That cost arrives whether or not revenue grows, so gross margin compresses unless utilization holds.

Year three: end demand softens, revenue falls to 70 billion, but the new depreciation is now in COGS. Gross margin compresses to roughly 46 percent. Capex is cut to 18 billion. Book-to-bill falls below 1.0 at WFE suppliers. Equipment makers (Applied Materials, Lam Research, Tokyo Electron, ASML) report declining bookings. The cycle is in the down phase.

Common Mistakes

1. Reading capex announcements as bullish without context. A capex hike during peak utilization signals confidence; the same hike at the end of a long upcycle signals over-investment. Always scale capex against the recent revenue trend and capacity utilization.

2. Ignoring the lag between WFE orders and silicon output. Equipment order strength today translates to silicon output 12 to 24 months later. Confusing the order signal with the production signal causes timing errors when forecasting end-market supply.

3. Conflating leading-edge with lagging-node demand. The cycle for 3 nm logic, mature 28 nm trailing-edge, and DRAM are not synchronized. A weak DRAM cycle can coexist with a strong leading-edge logic cycle, as occurred during the 2023-2024 AI accelerator surge per SIA and SEMI reporting.

4. Underestimating inventory destocking. When channel inventories build, distributor and customer destocking can suppress wafer demand for two to four quarters even after end demand stabilizes. Track inventory days at fabless customers (Nvidia, AMD, Qualcomm, Broadcom) as the early warning.

5. Ignoring policy capex. The U.S. CHIPS Act, EU Chips Act, and similar policies subsidize capex that would not otherwise clear the IRR test. Subsidized capacity can extend the upcycle artificially and deepen the next downcycle. Read footnotes on government grants and tax credits in 10-K filings.

Frequently Asked Questions

Q: What is the semiconductor capex cycle in simple terms? The semiconductor capex cycle is the recurring pattern of investment expansion and contraction in fab capacity and equipment. During an upcycle, foundries and IDMs ramp capex to 20–25 percent of revenue to meet demand; in a downturn, they cut to 10 percent or below as customers work down excess inventory. The cycle runs roughly three to four years from peak to peak and is tracked through wafer fab equipment (WFE) orders from SEMI.

Q: How does the semiconductor capex cycle affect investment decisions? The cycle determines margin trajectories for foundries, equipment makers, memory companies, and downstream chip designers. WFE order trends from SEMI provide a 12–24 month leading signal for when new supply will hit the market. Equipment makers (ASML, Applied Materials, Lam Research) benefit most in the early upcycle; foundries and IDMs benefit in the mid-cycle as new capacity is fully utilized; fabless companies benefit in the downcycle as pricing normalizes.

Q: What is a real-world example of semiconductor capex cycle analysis? In the worked example, a foundry with $60 billion revenue at 23 percent capital intensity announces $30 billion capex in year two, lifting intensity to 40 percent for a major node ramp. By year three, the new depreciation adds $5 billion annually to COGS while revenue softens to $70 billion, compressing gross margin from 53 to roughly 46 percent. WFE suppliers report book-to-bill below 1.0, the classic early-downcycle signal.

Q: How can investors use semiconductor capex cycle analysis? Track WFE book-to-bill from SEMI quarterly as the earliest signal of cycle direction. Monitor inventory days at fabless customers like Nvidia, AMD, and Qualcomm, rising inventory there precedes deceleration of wafer orders by one to two quarters. Scale capex announcements against current utilization to determine whether the investment signals confidence or over-expansion, and check for government grant disclosures that may be subsidizing capacity beyond economic demand.

Q: How is the semiconductor capex cycle different from the AI capex cycle? The semiconductor capex cycle is the broader industry pattern of fab capacity investment covering all end markets, mobile, PC, industrial, automotive, and data center. The AI capex cycle is the demand-side acceleration from hyperscalers specifically, concentrated on leading-edge logic and high-bandwidth memory. The AI cycle is running inside the semiconductor capex cycle, creating a bifurcation where leading-edge logic is in upcycle while mature nodes and memory face independent demand dynamics.

Sources

1. Semiconductor Industry Association. "Industry Statistics and Factbook." https://www.semiconductors.org/resources/
2. SEMI. "World Fab Forecast and Equipment Market Reports." https://www.semi.org/en/products-services/market-data
3. Taiwan Semiconductor Manufacturing Company Limited. Annual Report on Form 20-F. SEC EDGAR. https://www.sec.gov/cgi-bin/browse-edgar?action=getcompany&CIK=0001046179&type=20-F
4. Applied Materials, Inc. Annual Report on Form 10-K. SEC EDGAR. https://www.sec.gov/cgi-bin/browse-edgar?action=getcompany&CIK=0000006951&type=10-K

Disclaimer

This article is educational content only and is not financial advice. Nothing here is a recommendation to buy, sell, or hold any security. Consult a licensed advisor before making investment decisions.